- This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or...
- We propose a framework to unify the process of false paths and multi-cycle paths in static timing analysis (STA). We use subgraphs attached with timing constraints to represent f...
Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan...
Due to false paths and multi-cycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing a...
A novel algorithm for object tracking in video pictures, based on image segmentation and pattern matching, as well as its FPGA/ASIC implementation architecture are presented. With ...
K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tet...
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
Abstract-- This paper presents a fundamental result on buffer sizing. Given an interconnection wire with n buffers evenly spaced along the wire, we would like to size all buffers s...
- In this paper, we study the relationship between C4 package resonance effects and logical switching timing correlations, which has not been thoroughly investigated in the past. W...
Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hon...
- This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We me...
Kazuhiko Miki, David Boerstler, Eskinder Hailu, Ji...