Acceleration techniques for dynamic vector compaction

: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly improve the computation times without adversely affecting the quality of test sets that can be derived using stateof-the-art compaction methods. Our techniques are based on threekey ideas: (1) identification ofsupportsets, (2) targetfault switching, and (3) use of dynamic equivalent and untestable fault analysis. All these techniques are useful in significantly reducing the number of faults that have to be considered by a test generator or a fault simulator in a dynamic vector compaction system. For fault simulation, support sets quickly identify a large subset of faults that are guaranteed to be undetectable by a given input sequence. For test generation, supportsets identify a large subsetof faults that are guaranteed to be undetectable by any extension of a partially specified test sequence. Experimental ...

• Type: Conference
• Year: 1995
• Where: ICCAD
• Authors: Anand Raghunathan, Srimat T. Chakradhar
• Keywords: Computation Times, Dynamic Vector Compaction, Hardware, ICCAD 1995, Test Sets