An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators

This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many intervals. This time-division parallelization is similar to the concept of trace-splitting parallelization but is completely different from this conventional technique because our simulator assures that its result is perfectly equivalent to what a sequential simulator produces. The assurance of the perfect accuracy is endued by a simple failure recovery mechanism; if i-th interval is simulated by a node with an approximate initial machine state which causes invalid result, the interval is simulated again by the node responsible to (i-1)-th interval and thus having the correct state at the beginning of i-th interval. In order to reduce the possibility of the interval failure for efficiency, the fully cycleaccurate simulation for an interval is preceded by a partial and thus fast microarchitectural simulation inc...

• Type: Conference
• Year: 2007
• Where: ANSS
• Authors: Masahiro Yano, Toru Takasaki, Takashi Nakada, Hiroshi Nakashima
• Keywords: ANSS 2007, I-th Interval, Interval Failure, Modelling And Simulation, Simulations