Using TLM for Exploring Bus-based SoC Communication Architectures

As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design requirements in shrinking time-to-market windows, and have begun using an IP-based SoC design methodology that permits reuse of key SoC functional components. Since the communication architectures connecting components in these SoC designs significantly impact system performance, it is imperative that designers explore the communication design space efficiently, quickly and early in the design flow. Transaction Level Modeling an emerging abstraction that facilitates early exploration of SoC architectures. This paper outlines a typical IP-based SoC design flow, and presents the Cycle Count Accurate at Transaction Boundaries (CCATB) abstraction which is a fast, efficient and flexible approach for exploring bus-based communication architectures in SoC designs. The CCATB models not only take less time to model b...

• Type: Conference
• Year: 2005
• Where: ASAP
• Authors: Sudeep Pasricha, Mohamed Ben-Romdhane
• Keywords: ASAP 2005, Communication Architectures, Distributed And Parallel Computing, IP-based SoC Design, SoC Designs