Accurate Area, Time and Power Models for FPGA-Based Implementations

This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate efficient design space exploration in an automated algorithmarchitecture codesign framework. Detailed models for estimating the number of slices, block RAMs and 18x18-bit multipliers for fixed point and floating point IP cores have been developed. These models are also utilized to develop power models that consider the effect of logic power, signal power, clock power and I/O power. Timing models have been developed to predict the latency of the fixed point and floating point IP cores. In all cases, the model coefficients have been derived by using curve fitting or regression analysis. The modeling error is quite small for single IP cores; the error for the area estimate, for instance, is on the average 0.95%. The error for fairly large examples such as floating point implementation of 8-point FFTs

• Type: Journal
• Year: 2011
• Where: VLSISP
• Authors: Lanping Deng, Kanwaldeep Sobti, Yuanrui Zhang, Chaitali Chakrabarti
• Keywords: Database, IP Cores, Point Ip, VLSISP 2011, fixed Point