75 search results - page 1 / 15 » Accurate Area, Time and Power Models for FPGA-Based Implemen... |
VLSISP
2011
14 years 28 days ago
2011
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
ICASSP
2008
IEEE
15 years 13 days ago
2008
IEEE
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
ICCD
2005
IEEE
15 years 2 months ago
2005
IEEE
FPGA logic densities continue to increase at a tremendous rate. This has had the undesired consequence of increased power density, which manifests itself as higher ondie temperatu...
ICCAD
2008
IEEE
13 years 11 months ago
2008
IEEE
Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been pr...
WSC
1998
1998
Effective Implementation of Cycle Time Reduction Strategies for Semiconductor Back-end Manufacturing
14 years 7 months ago
Using discrete-event simulation models, a study was conducted to evaluate the current production practices of a high-volume semiconductor back-end operation. The overall goal was ...