This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
FPGA logic densities continue to increase at a tremendous rate. This has had the undesired consequence of increased power density, which manifests itself as higher ondie temperatu...
Sivakumar Velusamy, Wei Huang, John Lach, Mircea R...
Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been pr...
Using discrete-event simulation models, a study was conducted to evaluate the current production practices of a high-volume semiconductor back-end operation. The overall goal was ...
Joerg Domaschke, Steven Brown, Jennifer Robinson, ...