Adapting JTAG for AC Interconnect Testing

The use of AC coupled interconnects to provide communication paths between devices is increasing. The existing IEEE 1149.1 boundary scan standard [1] (JTAG) has limitations that hinder it from being able to effectively test all AC coupled interconnects. This paper describes a simple enhancement to the JTAG architecture enabling it to operate in new modes facilitating AC interconnect testing. Description Figure 1 illustrates a DC interconnect being tested using the existing JTAG standard. The DC interconnect includes an example termination element (R). In functional mode, a core output of a first device passes through a JTAG boundary cell and output buffer to be transmitted through the external DC interconnect to a core input of a second device, via an input buffer and JTAG boundary cell. In test mode, and during the JTAG Extest instruction, the boundary cells are controlled by the JTAG test access port (TAP) and instruction register to operate independent of the IC’s core circuitry ...

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Lee Whetsel
• Keywords: Boundary Cell, DC Interconnect, Hardware, ITC 2003, JTAG