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ITC 2003 International Test Conference

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ITC
2003
IEEE

327views Hardware» more ITC 2003»

Case Study - Using STIL as Test Pattern Language

14 years 5 months ago

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This paper describes the implementation of a test pattern language using STIL [1], the IEEE Standard Test Interface Language (1450-1999), in a next generation, open architecture A...

Daniel Fan, Steve Roehling, Rusty Carruth

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Id	Views	Title	Status

1	327	Case Study - Using STIL as Test Pattern Language	claim
2	276	Automatic Diagnostic Program Generation for Mixed Signal Load Board	claim
3	222	Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation	claim
4	214	ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume	claim
5	205	H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing	claim
6	197	Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA)	claim
7	183	Future Challenges for MEMS Failure Analysis	claim
8	181	Latch Divergency In Microprocessor Failure Analysis	claim
9	177	Analyzing the Effectiveness of Multiple-Detect Test Sets	claim
10	176	Instruction Based BIST for Board/System Level Test of External Memories and Internconnects	claim
11	172	First IC Validation of IEEE Std. 1149.6	claim
12	170	Double-Tree Scan: A Novel Low-Power Scan-Path Architecture	claim
13	168	A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy	claim
14	168	Agent Based DBIST/DBISR And Its Web/Wireless Management	claim
15	167	Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk	claim
16	163	Novel Transient Fault Hardened Static Latch	claim
17	162	FPGA Interconnect Delay Fault Testing	claim
18	162	Concurrent Error Detection in Linear Analog Circuits Using State Estimation	claim
19	161	DFFT : Design For Functional Testability	claim
20	158	Extraction Error Diagnosis and Correction in High-Performance Designs	claim
21	157	Parity-Based Concurrent Error Detection in Symmetric Block Ciphers	claim
22	156	A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation	claim
23	153	An Efficient and Effective Methodology on the Multiple Fault Diagnosis	claim
24	151	Fault Collapsing via Functional Dominance	claim
25	149	BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study	claim
26	149	On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures	claim
27	148	HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk	claim
28	148	Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs	claim
29	147	Data flow within an open architecture tester	claim
30	147	The Testability Features of The ARM1026EJ Microprocessor Core	claim
31	146	A New Approach for Low Power Scan Testing	claim
32	145	CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing	claim
33	145	MEMS Manufacturing Testing: An Accelerometer Case Study	claim
34	143	A Case Study of IR-Drop in Structured At-Speed Testing	claim
35	143	Designed -in-diagnostics: A new optical method	claim
36	141	Testability Features of the Alpha 21364 Microprocessor	claim
37	141	Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits	claim
38	139	Fault Pattern Oriented Defect Diagnosis for Memories	claim
39	139	A Hybrid Coding Strategy For Optimized Test Data Compression	claim
40	138	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint	claim
41	136	A BIST Solution for The Test of I/O Speed	claim
42	136	Adapting JTAG for AC Interconnect Testing	claim
43	135	VDD Ramp Testing for RF Circuits	claim
44	135	MEMS Design And Verification	claim
45	134	Effectiveness Improvement of ECR Tests	claim
46	132	Application of Built in Self-Test for Interconnect Testing of FPGAs	claim
47	132	Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions	claim
48	129	Relating Yield Models to Burn-In Fall-Out in Time	claim
49	127	Architecting Millisecond Test Solutions for Wireless Phone RFIC's	claim
50	127	Testing of Droplet-Based Microelectrofluidic Systems	claim
51	127	Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus	claim
52	127	Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects	claim
53	126	Impact of Multiple-Detect Test Patterns on Product Quality	claim
54	126	Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies	claim
55	126	Deformations of IC Structure in Test and Yield Learning	claim
56	126	Convolutional Compaction of Test Responses	claim
57	125	Progressive Bridge Identification	claim
58	124	Power-aware NoC Reuse on the Testing of Core-based Systems	claim
59	124	Low Contact-Force Fritting Probe Card Using Buckling Microcantilevers	claim
60	124	On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding	claim
61	124	Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ	claim
62	123	Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores	claim
63	123	A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic	claim
64	123	Hysteresis of Intrinsic IDDQ Currents	claim
65	122	EEPROM Memory: Threshold Voltage Built In Self Diagnosis	claim
66	120	High Quality ATPG for Delay Defects	claim
67	120	Test Vector Generation Based on Correlation Model for Ratio-Iddq	claim
68	119	Fault Localization using Time Resolved Photon Emission and STIL Waveforms	claim
69	119	Defect Tolerance at the End of the Roadmap	claim
70	118	Method of reducing contactor effect when testing high-precision ADCs	claim
71	118	Failure Mechanisms in MEMS	claim
72	116	Circular BIST testing the digital logic within a high speed Serdes	claim
73	116	BIST for Deep Submicron ASIC Memories with High Performance Application	claim
74	115	Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing	claim
75	115	Towards Structural Testing of Superconductor Electronics	claim
76	114	MEMS Fabrication	claim
77	114	Test-Based Model Generation For Legacy Systems	claim
78	114	RIC/DICMOS-- Multi-channel CMOS Formatter	claim
79	113	Fault Injection for Verifying Testability at the VHDL Level	claim
80	113	Simultaneous Bidirectional Test Data Flow for a Low-cost Wafer Test Strategy	claim
81	112	Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault	claim
82	110	An extension to JTAG for at-speed debug on a system	claim
83	109	The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data	claim
84	109	Tools and Techniques for Failure Analysis and Qualification of MEMS	claim
85	108	Backplane Test Bus Applications For IEEE STD 1149.1	claim
86	108	Optical and Electrical Testing of Latchup in I/O Interface Circuits	claim
87	107	The PXI Modular Instrumentation Architecture	claim
88	106	Detection of Resistive Shorts in Deep Sub-micron Technologies	claim
89	105	IEEE 1149.6 - A Practical Perspective	claim
90	104	On-line Detection of Faults in Carry-Select Adders	claim
91	103	Introduction to Applications and Industries for Microelectromechanical Systems (MEMS)	claim
92	102	Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices	claim
93	102	CMOS Built-In Test Architecture for High-Speed Jitter Measurement	claim
94	97	A Generic Test Path and DUT Model for DataCom ATE	claim
95	96	Key Impediments to DFT-Focused Test and How to Overcome Them	claim
96	94	A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling	claim
97	93	Hybrid Multisite Testing at Manufacturing	claim
98	93	On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs	claim
99	93	On Reducing Wrapper Boundary Register Cells in Modular SOC Testing	claim
100	92	Infrastructure IP for Back-End Yield Improvement	claim
101	90	Burn-in Temperature Projections for Deep Sub-micron Technologies	claim

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