Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis

On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the design of buffers in the router influences the energy consumption, area overhead, and overall performance of the network. In this paper, we propose a low-power low-area OCIN architecture by reducing the number of buffers within the router. To minimize the performance degradation due to the reduced buffer size, we use the already existing repeaters along the inter-router channels to double as buffers along the channel when required. At low network loads, the proposed adaptive channel buffers function as conventional repeaters, propagating the signals. At high network loads, the adaptive channel buffers function as storage elements in addition to the router buffers. The router buffers can be assigned either statically or dynamically to the incoming packets. Static allocation reserves equal buffer space partitio...

• Type: Journal
• Year: 2008
• Where: TC
• Authors: Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
• Keywords: Adaptive Channel Buffers, Dynamic Buffer Allocation, Information Technology, Router Buffer, TC 2008