Adaptive prefetching for shared cache based chip multiprocessors

Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based CMP, multiple cores compete for the shared on-chip cache space and limited off-chip pin bandwidth. Purely software based prefetching techniques tend to increase this contention, leading to degradation in performance. In some cases, prefetches can become harmful by kicking out useful data from the shared cache whose next usage is earlier than the prefetched data, and the fraction of such harmful prefetches usually increases when we increase the number of cores used for executing a multi-threaded application code. In this paper, we propose two complementary techniques to address the problem of harmful prefetches in the context of shared L2 based CMPs. These techniques, namely, suppressing select data prefetches (if they are found to be harmful) and pinning select data in the L2 cache (if they are found to be fr...

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: Mahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk
• Keywords: DATE 2009, Hardware, Harmful Prefetches, L2 Based Cmps, On-chip Cache Space