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DATE
2009
IEEE

249views Hardware» more DATE 2009»

White box performance analysis considering static non-preemptive software scheduling

14 years 6 months ago

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—In this paper, a novel approach for integrating static non-preemptive software scheduling in formal bottom-up performance evaluation of embedded system models is described. The ...

Alexander Viehl, Michael Pressler, Oliver Bringman...

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Id	Views	Title	Status

1	249	White box performance analysis considering static non-preemptive software scheduling	claim
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12	180	FSAF: File system aware flash translation layer for NAND Flash Memories	claim
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15	176	Single ended 6T SRAM with isolated read-port for low-power embedded systems	claim
16	176	Automated synthesis of streaming C applications to process networks in hardware	claim
17	172	On bounding response times under software transactional memory in distributed multiprocessor real-time systems	claim
18	171	Energy-efficient spatially-adaptive clustering and routing in wireless sensor networks	claim
19	171	Automatic generation of streaming datapaths for arbitrary fixed permutations	claim
20	171	Physically clustered forward body biasing for variability compensation in nanometer CMOS design	claim
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32	155	Dynamic thermal management in 3D multicore architectures	claim
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47	146	Heterogeneous multi-core platform for consumer multimedia applications	claim
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50	143	Dimensioning heterogeneous MPSoCs via parallelism analysis	claim
51	143	Time and memory tradeoffs in the implementation of AUTOSAR components	claim
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53	141	Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis	claim
54	141	Evaluation on FPGA of triple rail logic robustness against DPA and DEMA	claim
55	140	Lifetime reliability-aware task allocation and scheduling for MPSoC platforms	claim
56	140	Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors	claim
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58	139	Reliable mode changes in real-time systems with fixed priority or EDF scheduling	claim
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61	139	A flexible layered architecture for accurate digital baseband algorithm development and verification	claim
62	138	Semiformal verification of temporal properties in automotive hardware dependent software	claim
63	138	A novel self-healing methodology for RF Amplifier circuits based on oscillation principles	claim
64	138	Scalable Adaptive Scan (SAS)	claim
65	138	Hardware/software co-design architecture for thermal management of chip multiprocessors	claim
66	138	Cache aware compression for processor debug support	claim
67	138	An approximation scheme for energy-efficient scheduling of real-time tasks in heterogeneous multiprocessor systems	claim
68	137	aEqualized: A novel routing algorithm for the Spidergon Network On Chip	claim
69	137	A self-adaptive system architecture to address transistor aging	claim
70	137	Componentizing hardware/software interface design	claim
71	137	Adaptive prefetching for shared cache based chip multiprocessors	claim
72	136	A novel approach to entirely integrate Virtual Test into test development flow	claim
73	136	A file-system-aware FTL design for flash-memory storage systems	claim
74	136	Reconfigurable circuit design with nanomaterials	claim
75	135	Gate replacement techniques for simultaneous leakage and aging optimization	claim
76	135	System-level hardware-based protection of memories against soft-errors	claim
77	135	Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration	claim
78	134	Massively multi-topology sizing of analog integrated circuits	claim
79	134	Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures	claim
80	134	A diagnosis algorithm for extreme space compaction	claim
81	133	Pipelined data parallel task mapping/scheduling technique for MPSoC	claim
82	133	Energy efficient multiprocessor task scheduling under input-dependent variation	claim
83	133	Architectural support for low overhead detection of memory violations	claim
84	133	SecBus: Operating System controlled hierarchical page-based memory bus protection	claim
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89	131	Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling	claim
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94	129	Energy minimization for real-time systems with non-convex and discrete operation modes	claim
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99	129	Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network	claim
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113	124	Design and implementation of scalable, transparent threads for multi-core media processor	claim
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119	122	Analysis and optimization of NBTI induced clock skew in gated clock trees	claim
120	122	A highly resilient routing algorithm for fault-tolerant NoCs	claim
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122	122	Model-based synthesis and optimization of static multi-rate image processing algorithms	claim
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124	121	Remote measurement of local oscillator drifts in FlexRay networks	claim
125	120	Towards a formal semantics for the AADL behavior annex	claim
126	120	Overcoming limitations of the SystemC data introspection	claim
127	120	Optimizing data flow graphs to minimize hardware implementation	claim
128	119	On-chip communication architecture exploration for processor-pool-based MPSoC	claim
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132	119	Statistical fault injection: Quantified error and confidence	claim
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137	118	Variation resilient adaptive controller for subthreshold circuits	claim
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148	114	Hardware aging-based software metering	claim
149	114	Formal approaches to analog circuit verification	claim
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172	109	The influence of real-time constraints on the design of FlexRay-based systems	claim
173	108	On the efficient reduction of complete EM based parametric models	claim
174	107	User-centric design space exploration for heterogeneous Network-on-Chip platforms	claim
175	107	Learning early-stage platform dimensioning from late-stage timing verification	claim
176	107	Sequential logic rectifications with approximate SPFDs	claim
177	106	Optimal sizing of configurable devices to reduce variability in integrated circuits	claim
178	106	A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing	claim
179	106	Debugging of Toffoli networks	claim
180	106	Generation of compact test sets with high defect coverage	claim
181	105	Enrichment of limited training sets in machine-learning-based analog/RF test	claim
182	105	UMTS MPSoC design evaluation using a system level design framework	claim
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225	89	Robust non-preemptive hard real-time scheduling for clustered multicore platforms	claim
226	89	Exploiting clock skew scheduling for FPGA	claim
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228	88	Rewiring using IRredundancy Removal and Addition	claim
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230	88	Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling	claim
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232	87	Multi-clock Soc design using protocol conversion	claim
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