An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design

This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement. This adaptive supply-voltage scheme employs the handshake signals directly to detect the speed of data path without using FIFO buffer. This leads to a very simple logic control whose power loss is negligible. Cadence SPICE simulation shows the effectiveness of this scheme for low power applications based on 0.18?m CMOS process.

• Type: Conference
• Year: 2003
• Where: VLSID
• Authors: W. Kuang, J. S. Yuan
• Keywords: Adaptive Supply-voltage Scheme, Computer Architecture, Low Power Applications, Low Power Performance, VLSID 2003