Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs

An exclusive-OR transform of input variables significantly reduces the size of the PLA implementation for adder and comparator circuits. For n bit adder circuits, the size of PLA for transformed functions is O(n2). In comparison, when the complete truth-table of an adder is minimized, the PLA size will be O(2n+2). Similarly, for an n bit comparator, the size of the PLA is reduced from O(2n+1) to O(n). Z’hese implementations require additional transform logic of complexity O(n), consisting of exclusive-OR gates. x2XnYl fT

• Type: Conference
• Year: 1997
• Where: VLSID
• Authors: James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal
• Keywords: Bit Adder, PLA Implementation, PLA Size, VLSI, VLSID 1997