Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation

With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal component of ESL tools to simulate the hardware designs and software models concurrently. It helps in providing an integrated system-on-chip design platform to get rid of most of the design errors in the early stage. To nail down these design errors early, a better debugging support of RTL memory on the software side is extremely useful. We present a just-in-time shadow memory technique that can allow debugging of RTL memory from a software perspective. While cosimulation is fast compared to a complete hardware based simulation, the communication and synchronization overhead between the hardware and software simulators can be very significant. Since the two simulators have to communicate almost every cycle, a good communication platform is necessary to reduce this extra overhead. To evaluate this overhead, w...

• Type: Conference
• Year: 2008
• Where: VLSID
• Authors: Banit Agrawal, Timothy Sherwood, Chulho Shin, Simon Yoon
• Keywords: Communication Overhead, Computer Architecture, Just-in-time Shadow Memory, RTL Memory, VLSID 2008