Analysis and design of low-phase-noise ring oscillators

This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is −114dBc/Hz at a 600kHz offset from the 960MHz carrier frequency.

• Type: Conference
• Year: 2000
• Where: ISLPED
• Authors: Liang Dai, Ramesh Harjani
• Keywords: Hardware, ISLPED 2000, Oscillator Phase Noise, Phase Noise, Phase Noise Model