Analysis and Detection of Timing Failures in an Experimental Test Chip

A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimental results were presented at ITC'95. This paper presents results for different clock speeds and clocking modes (at-speed and delay), and uses this data to characterize the behavior of the defective parts. It was found that timing-related defects are common, and the escape rate for different test techniques on these parts is discussed.

• Type: Conference
• Year: 1996
• Where: ITC
• Authors: Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin Chu, Sanjay Wattal, Edward J. McCluskey, Robert L. Stokes, William D. Farwell
• Keywords: Defective Parts, Gate Test Chip, Hardware, ITC 1996, Scan-designed Circuits