Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis

—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection techniques, including logic implication-based checker hardware, are capable of detecting at least some of these errors as they occur. However, recovery may be expensive, and the underlying problem may lead to multiple failures of a core over time. In this paper, we will investigate the diagnostic ability of logic implications to pinpoint possible failure locations when an error is detected online. We will then utilize this information to select highly efficient test sets that can be used to effectively test the identified suspect locations in both the failing core and in other identical cores in the system.

• Type: Journal
• Year: 2011
• Where: ETS
• Authors: Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar
• Keywords: Error Detection Techniques, ETS 2011, Feature Sizes, Hardware, Logic Implications