Analysis and minimization of practical energy in 45nm subthreshold logic circuits

Abstract— Over the last decade, the design of ultra-lowpower digital circuits in subthreshold regime has been driven by the quest for minimum energy per operation. In this contribution, we observe that operating at minimum-energy point is not straightforward as design constraints from real-life applications have an important impact on energy. Therefore, we introduce the alternative concept of practical energy, taking functional-yield and throughput constraints on minimum Vdd into account. In this context, we demonstrate for the first time the detrimental impact of DIBL on minimum Vdd. Practical energy gives a useful analysis framework of circuit optimization to reach minimum-energy point, while considering the throughput as an input variable dictated by the application. From simulation of a benchmark multiplier in 45nm technology, we find out that practical energy can be far higher than minimum energy point, in the case of lowthroughput applications (≈ 10-100 kOp/s) because of st...

• Type: Conference
• Year: 2008
• Where: ICCD
• Authors: David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat
• Keywords: Energy Meet Minimum, Hardware, ICCD 2008, Minimum Energy Level, Minimum Energy Point