ICCD 2008 - PDF Preprint Papers

ICCD 2008 International Conference on Computer Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ICCD-2008 Paper

click to vote

ICCD
2008
IEEE

498views Hardware» more ICCD 2008»

Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW

14 years 8 months ago

Download www.ece.uc.edu

— Run-time Active Leakage Reduction (RALR) is a recent technique and aims at aggressively reducing leakage power consumption. This paper studies the feasibility of RALR from the ...

Hao Xu, Ranga Vemuri, Wen-Ben Jone

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	498	Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW	claim
2	420	Frequency and voltage planning for multi-core processors under thermal constraints
3	370	Simulation points for SPEC CPU 2006	claim
4	221	Reversi: Post-silicon validation system for modern microprocessors	claim
5	204	Bridging the gap between nanomagnetic devices and circuits	claim
6	202	CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework	claim
7	194	Understanding performance, power and energy behavior in asymmetric multiprocessors	claim
8	192	Energy-aware opcode design	claim
9	191	Energy-delay tradeoffs in 32-bit static shifter designs	claim
10	175	Contention-aware application mapping for Network-on-Chip communication architectures	claim
11	175	On-chip high performance signaling using passive compensation	claim
12	167	Exploiting spare resources of in-order SMT processors executing hard real-time threads	claim
13	165	Analysis and minimization of practical energy in 45nm subthreshold logic circuits	claim
14	163	Low-cost open-page prefetch scheduling in chip multiprocessors	claim
15	160	Fast arbiters for on-chip network switches	claim
16	160	An improved micro-architecture for function approximation using piecewise quadratic interpolation	claim
17	159	Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor	claim
18	159	A high-performance parallel CAVLC encoder on a fine-grained many-core system	claim
19	158	Design and evaluation of an optical CPU-DRAM interconnect	claim
20	157	Power-aware soft error hardening via selective voltage scaling	claim
21	151	Digital filter synthesis considering multiple adder graphs for a coefficient	claim
22	150	Timing analysis considering IR drop waveforms in power gating designs	claim
23	148	Adaptive SRAM memory for low power and high yield	claim
24	146	Chip level thermal profile estimation using on-chip temperature sensors	claim
25	142	Making register file resistant to power analysis attacks	claim
26	142	Gate planning during placement for gated clock network	claim
27	139	Probabilistic error propagation in logic circuits using the Boolean difference calculus	claim
28	136	A resource efficient content inspection system for next generation Smart NICs	claim
29	133	Reliability-aware Dynamic Voltage Scaling for energy-constrained real-time embedded systems	claim
30	130	A dynamic accuracy-refinement approach to timing-driven technology mapping	claim
31	126	Accelerating search and recognition with a TCAM functional unit	claim
32	124	Global bus route optimization with application to microarchitectural design exploration	claim
33	122	Acquiring an exhaustive, continuous and real-time trace from SoCs	claim
34	121	Characterization and design of sequential circuit elements to combat soft error	claim
35	120	Near-optimal oblivious routing on three-dimensional mesh networks	claim
36	120	Improved combined binary/decimal fixed-point multipliers	claim
37	119	Hierarchical simulation-based verification of Anton, a special-purpose parallel machine	claim
38	118	Adaptive techniques for leakage power management in L2 cache peripheral circuits	claim
39	117	Two dimensional highly associative level-two cache design	claim
40	117	RMA: A Read Miss-Based Spin-Down Algorithm using an NV cache	claim
41	116	Prototyping a hybrid main memory using a virtual machine monitor	claim
42	115	Techniques for increasing effective data bandwidth	claim
43	111	Test-access mechanism optimization for core-based three-dimensional SOCs	claim
44	111	Power switch characterization for fine-grained dynamic voltage scaling	claim
45	109	Suitable cache organizations for a novel biomedical implant processor	claim
46	102	Seamless sequence of software defined radio designs through hardware reconfigurability of FPGAs	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers