Analysis of Queueing Displacement Using Switch Port Speedup

Current high-speed packet switching systems, ATM in particular, have large port buering requirements. The use of highly integrated ASIC technology for implementing high-degree and high-speed switch fabrics is facing a technology mismatch in the sense that today's chip technology does not allow to integrate on-chip the high-speed switching fabric with the large buering requirements. Consequently, many designs are based on the principles of queueing displacement, i.e., they attempt to move the queueing point o-chip. This is usually done by considerably speeding-up the on-chip switch output ports and placing a second external stage of buering between the switch fabric and the outgoing link circuitry. Such designs are very popular and are used by many current ATM switch vendors. While such schemes are widely used, no rigorous analysis has so far been oered to evaluate the design trade-os and to quantify the design points. The model we use to analyze the performance of the above...

• Type: Conference
• Year: 1997
• Where: INFOCOM
• Authors: Israel Cidon, Asad Khamisy, Moshe Sidi
• Keywords: Bu Er, Bu Ering Requirements, Communications, External Bu Er, INFOCOM 1997