Analysis of timing jitter in ring oscillators due to power supply noise

∑= += N i firiT 1 0 )( ττ (1) This paper presents a time-domain method for estimating the jitter in ring oscillators that is due to power supply noise. The method is used to analyze and compare the RMS cycle-to-cycle jitter of ring oscillators constructed from three possible delay elements: a CMOS digital inverter, a differential pair, and a current steering logic (CSL) inverter. Spice simulations verify the analysis method, and the results indicate that both the differential pair and CSL inverter provide superior supply noise immunity to the CMOS digital inverter. Figure 1: Time Domain Model for a 3-Stage Ring Oscillator

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Tony Pialis, Khoman Phang
• Keywords: CMOS Digital Inverter, CSL Inverter, ISCAS 2003, Ring Oscillator