Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective

CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper, a general comprehensive stochastic model of the power/ground (P/G) noise in VLSI circuits is presented. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise. The PLL timing jitter is predicted in response to the VCO phase noise. Next, the design of a low power, 2.5V, 0.25µ CMOS PLL clock generator with a lock range of 100MHz-400MHz is described. Our mathematical method is utilized to study the jitter-induced P/G noise in this PLL. A comparison between the results obtained by our mathematical model and those obtained by HSPICE simulation prove the accuracy of the predicted model.

• Type: Conference
• Year: 2001
• Where: ICCD
• Authors: Payam Heydari, Massoud Pedram
• Keywords: CMOS PLL Clock, Hardware, ICCD 2001, Phase Noise, PLL Timing Jitter