An analytical placer for mixed-size 3D placement

Existing 3D placement techniques are mainly used for standardcell circuits, while mixed-size placement is needed to support highlevel functional units and intellectual property (IP) blocks. In this paper we present an analytical 3D placement method that is capable of placing mixed-size circuits. A multiple-stepsize scheme for the analytical solver is proposed to handle standard cells and macros differently for stability and efficiency. To relieve the difficulty of legalization, 3D floorplan-based initial solutions are used to guide the analytical solver. As far as we know, this is the first work that reports 3D placement results for mixed-size circuits. Our experiments show that the multiple-stepsize scheme is better than single-stepsize schemes in both quality and runtime. The experimental results on the ICCAD’04 mixed-size benchmarks show that the 4-tier 3D mixed-size placement can reduce the wirelength by 27% on average compared to 2D placement. The results also show that the 3D ...

• Type: Conference
• Year: 2010
• Where: ISPD
• Authors: Jason Cong, Guojie Luo
• Keywords: Analytical 3D Placement, Hardware, ISPD 2010, Mixed-size Circuits, Mixed-size Placement