Analyzing the trade-off between multiple memory controllers and memory channels on multi-core processor performance

Increasing the core-count on current and future processors is posing critical challenges to the memory subsystem to efficiently handle concurrent memory requests. The current trend to cope with this challenge is to increase the number of memory channels available to the processor's memory controller. In this paper we investigate the effectiveness of this approach on the performance of parallel scientific applications. Specifically, we explore the trade-off between employing multiple memory channels per memory controller and the use of multiple memory controllers. Experiments conducted on two current state-of-the-art multicore processors, a 6-core AMD Istanbul and a 4core Intel Nehalem-EP, for a wide range of production applications shows that there is a diminishing return when increasing the number of memory channels per memory controller. In addition, we show that this performance degradation can be efficiently addressed by increasing the ratio of memory controllers to channels ...

• Type: Journal
• Year: 2010
• Where: IPPS
• Authors: José Carlos Sancho, Michael Lang 0003, Darren J. Kerbyson
• Keywords: Distributed And Parallel Computing, IPPS 2010, Memory Channels, Memory Controllers, Multiple Memory