Application mapping for chip multiprocessors

The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, processor mapping, data mapping, and packet routing. In the first step, the application code is parallelized and the resulting parallel threads are assigned to virtual processors. The second step implements a virtual processor-to-physical processor mapping. The goal of this mapping is to ensure that the threads that are expected to communicate frequently with each other are assigned to neighboring processors as much as possible. In the third step, data elements are mapped to memories attached to CMP nodes. The main objective of this mapping is to place a given data item into a node which is close to the nodes that access it. The last step of our approach determines the paths (between memories and processors) for data to travel in an e...

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. Kandemir
• Keywords: Application Mapping, Computer Architecture, DAC 2008, Processor Mapping, Processor-to-physical Processor Mapping