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DAC
2008
ACM

228views Computer Architecture» more DAC 2008»

SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models

15 years 1 months ago

Download www12.informatik.uni-erlangen.de

SystemCoDesigner is an ESL tool developed at the University of Erlangen-Nuremberg, Germany. SystemCoDesigner offers a fast design space exploration and rapid prototyping of behavi...

Christian Haubelt, Thomas Schlichter, Joachim Kein...

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Id	Views	Title	Status

1	228	SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models	claim
2	214	Parallel programming: can we PLEASE get it right this time?	claim
3	204	Analog parallelism in ring-based VCOs	claim
4	193	Programmable logic circuits based on ambipolar CNFET	claim
5	191	Functional test selection based on unsupervised support vector analysis	claim
6	187	Daedalus: toward composable multimedia MP-SoC design	claim
7	187	Stochastic modeling of a thermally-managed multi-core system	claim
8	186	Type-matching clock tree for zero skew clock gating	claim
9	186	An 8x8 run-time reconfigurable FPGA embedded in a SoC	claim
10	182	Study of the effects of MBUs on the reliability of a 150 nm SRAM device	claim
11	179	SHIELD: a software hardware design methodology for security and reliability of MPSoCs	claim
12	177	Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM	claim
13	172	MAPS: an integrated framework for MPSoC application parallelization	claim
14	172	Partial order reduction for scalable testing of systemC TLM designs	claim
15	171	A progressive-ILP based routing algorithm for cross-referencing biochips	claim
16	170	Symbolic noise analysis approach to computational hardware optimization	claim
17	170	DeFer: deferred decision making enabled fixed-outline floorplanner	claim
18	169	Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation	claim
19	168	Faster symmetry discovery using sparsity of symmetries	claim
20	166	Predictive runtime verification of multi-processor SoCs in SystemC	claim
21	166	Concurrent topology and routing optimization in automotive network integration	claim
22	163	Predictive dynamic thermal management for multicore systems	claim
23	163	Technology exploration for graphene nanoribbon FETs	claim
24	162	Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction	claim
25	160	Latency and bandwidth efficient communication through system customization for embedded multiprocessors	claim
26	160	Bounded-lifetime integrated circuits	claim
27	157	Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement	claim
28	154	Predictive design space exploration using genetically programmed response surfaces	claim
29	152	Scan chain clustering for test power reduction	claim
30	151	Control theory-based DVS for interactive 3D games	claim
31	151	IntellBatt: towards smarter battery design	claim
32	149	Automatic synthesis of clock gating logic with controlled netlist perturbation	claim
33	148	Construction of concrete verification models from C++	claim
34	146	Miss reduction in embedded processors through dynamic, power-friendly cache design	claim
35	146	Bi-decomposing large Boolean functions via interpolation and satisfiability solving	claim
36	146	The synthesis of robust polynomial arithmetic with stochastic logic	claim
37	145	Enhancing timing-driven FPGA placement for pipelined netlists	claim
38	145	Design of high performance pattern matching engine through compact deterministic finite automata	claim
39	144	DeMOR: decentralized model order reduction of linear networks with massive ports	claim
40	143	Driver waveform computation for timing analysis with multiple voltage threshold driver models	claim
41	143	Tera-scale computing and interconnect challenges	claim
42	142	A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip	claim
43	142	On the role of timing masking in reliable logic circuit design	claim
44	141	Specify-explore-refine (SER): from specification to implementation	claim
45	140	Transistor level gate modeling for accurate and fast timing, noise, and power analysis	claim
46	139	Protecting bus-based hardware IP by secret sharing	claim
47	138	Multithreaded simulation for synchronous dataflow graphs	claim
48	138	Parameterized timing analysis with general delay models and arbitrary variation sources	claim
49	136	Feedback-controlled reliability-aware power management for real-time embedded systems	claim
50	136	Tunneling and slicing: towards scalable BMC	claim
51	133	Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness	claim
52	133	Forbidden transition free crosstalk avoidance CODEC design	claim
53	132	A MIPS R2000 implementation	claim
54	132	Cache modeling in probabilistic execution time analysis	claim
55	132	Variation-adaptive feedback control for networks-on-chip with multiple clock domains	claim
56	132	Application mapping for chip multiprocessors	claim
57	131	Automated transistor sizing for FPGA architecture exploration	claim
58	131	An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing	claim
59	131	Energy-optimal software partitioning in heterogeneous multiprocessor embedded systems	claim
60	130	Flow engineering for physical implementation: theory and practice	claim
61	130	A framework for block-based timing sensitivity analysis	claim
62	129	Low power passive equalizer optimization using tritonic step response	claim
63	128	Techniques for fully integrated intra-/inter-chip optical communication	claim
64	127	Topology synthesis of analog circuits based on adaptively generated building blocks	claim
65	125	Multiprocessor performance estimation using hybrid simulation	claim
66	124	Path smoothing via discrete optimization	claim
67	124	A power and temperature aware DRAM architecture	claim
68	124	Design and CAD for 3D integrated circuits	claim
69	123	Compiler-driven register re-assignment for register file power-density and temperature reduction	claim
70	121	Functionally linear decomposition and synthesis of logic circuits for FPGAs	claim
71	120	Run-time instruction set selection in a transmutable embedded processor	claim
72	120	Stochastic integral equation solver for efficient variation-aware interconnect extraction	claim
73	120	Temperature management in multiprocessor SoCs using online learning	claim
74	120	Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips	claim
75	119	The design of a low power carbon nanotube chemical sensor system	claim
76	118	ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction	claim
77	116	TuneFPGA: post-silicon tuning of dual-Vdd FPGAs	claim
78	115	ADAM: run-time agent-based distributed application mapping for on-chip communication	claim
79	113	Keeping hot chips cool: are IC thermal problems hot air?	claim
80	112	IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors	claim
81	112	Next generation wireless-multimedia devices: who is up for the challenge?	claim
82	111	The mixed signal optimum energy point: voltage and parallelism	claim
83	110	Characterizing chip-multiprocessor variability-tolerance	claim
84	110	Automated hardware-independent scenario identification	claim
85	109	DVFS in loop accelerators using BLADES	claim
86	109	An integrated nonlinear placement framework with congestion and porosity aware buffer planning	claim
87	106	On reliable modular testing with vulnerable test access mechanisms	claim
88	106	SystemVerilog implicit port enhancements accelerate system design & verification	claim
89	105	FPGA area reduction by multi-output function based sequential resynthesis	claim
90	103	Scalable min-register retiming under timing and initializability constraints	claim
91	102	Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts	claim
92	102	Merging nodes under sequential observability	claim
93	101	Topological routing to maximize routability for package substrate	claim
94	101	An efficient incremental algorithm for min-area retiming	claim
95	101	Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications	claim
96	98	Robust chip-level clock tree synthesis for SOC designs	claim
97	98	Federation: repurposing scalar cores for out-of-order instruction issue	claim
98	97	Parallelizing CAD: a timely research agenda for EDA	claim
99	96	Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs	claim
100	90	Formal datapath representation and manipulation for implementing DSP transforms	claim
101	87	A practical reconfigurable hardware accelerator for Boolean satisfiability solvers	claim
102	84	Many-core design from a thermal perspective	claim
103	81	Efficient system design space exploration using machine learning techniques	claim

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