Applying Decay Strategies to Branch Predictors for Leakage Energy Savings

With technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large onchip array structures such as caches and branch predictors. Recent work has suggested that even larger branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that the branch predictor is a thermal hot spot, thus further increasing its leakage. For these reasons, it is natural to consider applying decay techniques—already shown to reduce leakage energy for caches—to branch-prediction structures. Due to the structural difference between caches and branch predictors, applying decay techniques to branch predictors is not straightforward. This paper explores the strategies for exploiting spatial and temporal locality to make decay effective for bimodal, gshare, and hybrid predictors, as well as the branch target buffer. Overall, this paper demonstrates that decay techniques apply more broadly than just to caches, b...

• Type: Conference
• Year: 2002
• Where: ICCD
• Authors: Zhigang Hu, Philo Juang, Kevin Skadron, Douglas W. Clark, Margaret Martonosi
• Keywords: Branch Predictors, Decay-based Branch Predictors, Hardware, ICCD 2002, Larger Branch Predictors