Architectural approaches to reduce leakage energy in caches

In this paper, we present two methods to reduce leakage energy by dynamically resizing the cache during program execution. The first method monitors the miss rate of the individual subbanks (in a subbanked cache structure) and selectively shuts them if their miss rate falls below a predetermined threshold. Simulations on SPECJVM98 benchmarks show that for a 64K Icache, this method results in a leakage reduction of 17-69% for a 4 subbank structure and 18-75% for a 8 subbank structure when the performance penalty is <1%. The second method dynamically resizes the cache based on whether the macroblocks (a group of adjacent cache blocks) are being heavily accessed or not. This method has higher area overhead but greater leakage energy reduction. Simulations on the same set of benchmarks show that this method results in a leakage reduction of 22-81% for the I-cache when the performance penalty is <0.1%, and 17-85% for the D-cache when the performance penalty is <1%.

• Type: Conference
• Year: 2002
• Where: ISCAS
• Authors: S. H. Tadas, C. Chakrabarti
• Keywords: Hardware, ISCAS 2002, Leakage Energy, Leakage Reduction, Performance Penalty