ISCAS 2002 - PDF Preprint Papers

ISCAS 2002 International Symposium on Circuits and Systems

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ISCAS
2002
IEEE

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Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization

14 years 5 months ago

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Arkadiy Morgenshtein, Alexander Fish, Israel A. Wa...

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Id	Views	Title	Status

1	737	Gate-diffusion input (GDI) - a technique for low power design of digital circuits: analysis and characterization	claim
2	213	Canny edge based image expansion	claim
3	201	FGS+: optimizing the joint SNR-temporal video quality in MPEG-4 fine grained scalable coding	claim
4	195	A low-power, low-noise CMOS amplifier for neural recording applications	claim
5	190	A high performance JPEG2000 architecture	claim
6	190	Analysis and improvement of correlation-based watermarking methods for digital images	claim
7	188	An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications	claim
8	172	Constant quality rate control for streaming MPEG-4 FGS video	claim
9	171	A robust frequency compensation scheme for LDO regulators	claim
10	163	A two-pass optimal motion-threading technique for 3D wavelet video coding	claim
11	154	Architectural approaches to reduce leakage energy in caches	claim
12	153	Biological learning modeled in an adaptive floating-gate system	claim
13	149	Adaptive end-to-end optimization of mobile video streaming using QoS negotiation	claim
14	149	Design of a DSP-based 24 bit digital audio equalizer for automotive applications	claim
15	143	Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000	claim
16	141	Power characterization of digital filters implemented on FPGA	claim
17	139	Mobility support for Bluetooth public access	claim
18	132	Lossless/lossy coding gain to evaluate coding performance of the lossless/lossy wavelet	claim
19	130	Analysis of limit cycle stability in a tap-changing transformer	claim
20	125	Switching activity estimation of finite state machines for low power synthesis	claim
21	124	Performance optimization of multiple memory architectures for DSP	claim
22	123	Blind electromagnetic source separation and localization	claim
23	121	Complex modulated critically sampled filter banks based on cosine and sine modulation	claim
24	121	Analog filter adaptation using a dithered linear search algorithm	claim
25	118	Adaptive playout for real-time media streaming	claim
26	118	A curvature compensation technique for bandgap voltage references using adaptive reference temperature	claim
27	118	A power-configurable bus for embedded systems	claim
28	116	Antisymmetries in the realization of Boolean functions	claim
29	116	A coefficient memory addressing scheme for VLSI implementation of FFT processors	claim
30	116	Automatic tuning of linearly tunable high-Q filters	claim
31	114	Lossless, near-lossless and lossy adaptive coding based on the lossless DCT	claim
32	114	Concept of frequency-transconductance tuning of bipolar voltage-controlled oscillators	claim
33	113	Chaotic optimization for quadratic assignment problems	claim
34	113	Cell library for automatic synthesis of analog error control decoders	claim
35	112	5th order multi-tone Volterra simulator with component-level output	claim
36	112	An adaptive analog video line driver with impedance matching based on peak detection	claim
37	112	Tradeoff analysis of FPGA based elliptic curve cryptography	claim
38	111	CASCADE - configurable and scalable DSP environment	claim
39	110	Incorporation of input glitches into power macromodeling	claim
40	110	Stochastic resonance of a threshold detector: image visualization and explanation	claim
41	110	Asymmetry half bridge soft-switching PFC converter with direct energy transfer	claim
42	109	State space blind source recovery for mixtures of multiple source distributions	claim
43	108	Optimal adaptive bandwidth monitoring for QoS based retrieval	claim
44	107	H.26L-based fine granularity scalable video coding	claim
45	104	High-speed add-compare-select units using locally self-resetting CMOS	claim
46	103	Third-generation and beyond (3.5G) wireless networks and its applications	claim
47	103	A SPICE model for single electronics	claim
48	102	Minimax design of 2-D IIR digital filters using sequential semidefinite programming	claim
49	102	A SET quantizer circuit aiming at digital communication system	claim
50	101	Empirical comparison of analog and digital auditory preprocessing for automatic speech recognition	claim
51	100	Continuous-time linear systems: folklore and fact	claim
52	99	An analog-to-digital converter with time-variant window	claim
53	98	Analysis of Hopf bifurcation in parallel-connected boost converters via averaged models	claim
54	97	High-frequency dynamic translinear and log-domain circuits in CMOS technology	claim
55	97	A new pipelined adaptive DFE architecture with improved convergence rate	claim
56	97	Block loss recovery in DCT image encoding using POCS	claim
57	96	Analysis of interleaved converters with WTA-based switching	claim
58	96	Low-power circuit advantages of the scaled accumulation FET	claim
59	95	A differential DAC architecture with variable common-mode level	claim
60	95	Lossless wavelet image coding using layered coefficient partitioning	claim
61	95	A CMOS imager with real-time frame differencing and centroid computation	claim
62	94	Video transport over ad-hoc networks using multiple paths	claim
63	94	Minimum power broadcast trees for wireless networks: optimizing using the viability lemma	claim
64	94	Wavelet method for high-speed clock tree simulation	claim
65	94	Modeling hot-electrons effects in silicon-on-sapphire MOSFETs	claim
66	94	A robust self-resetting CMOS 32-bit parallel adder	claim
67	94	RF gain control in direct conversion receivers	claim
68	93	A 14-bit, 40-MS/s DAC with current mode deglitcher	claim
69	93	Real-time streaming for the animation of talking faces in multiuser environments	claim
70	93	Time-frequency analysis in power measurement using complex wavelets	claim
71	92	Low cost floating-point unit design for audio applications	claim
72	92	Dynamic throughput estimation for wireless multimedia transmission	claim
73	92	Statistical analysis of power spectra of signals governed by Markov chains	claim
74	91	Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)	claim
75	91	Lossless/lossy image compression based on non-separable two-dimensional L-SSKF	claim
76	91	Efficient digit-serial FIR filters with skew-tolerant domino	claim
77	91	Charge-based MOS correlated double sampling comparator and folding circuit	claim
78	90	Design of oversampling current steering DAC with 640 MHz equivalent clock frequency	claim
79	90	Low complexity OFDM receiver using Log-FFT for coded OFDM system	claim
80	90	Comparative analysis of double-edge versus single-edge triggered clocked storage elements	claim
81	90	An improved Q-tuning scheme and a fully symmetric OTA	claim
82	89	On segmented channel routability	claim
83	89	Seamless switching of scalable video bitstreams for efficient streaming	claim
84	89	Mapping the wavelet transform onto silicon: the dynamic translinear approach	claim
85	89	ESD protection circuits with novel MOS-bounded diode structures	claim
86	88	Low depth carry lookahead addition using charge recycling threshold logic	claim
87	88	A multistage filterbank-based channelizer and its multiplier-less realization	claim
88	88	Energy dissipation modeling of lossy transmission lines driven by CMOS inverters	claim
89	87	Transient bit error rate analysis of data recovery systems using jitter models	claim
90	87	An automatic tuning scheme for high frequency bandpass filters	claim
91	87	Systolic architectures for finite field inversion and division	claim
92	87	A high throughput context-based adaptive arithmetic codec for JPEG2000	claim
93	86	On the optimal labeling for pseudo-chaotic phase hopping	claim
94	85	The Cauchy-Floquet factorization by successive Riccati transformations	claim
95	85	Automated test development and test time reduction for RF subsystems	claim
96	85	A wide-linear-range subthreshold CMOS transconductor employing the back-gate effect	claim
97	85	Tunable floating-gate low-voltage transconductor	claim
98	85	Low power implementation of high throughput FIR filters	claim
99	85	Design trade-offs of a symmetric linearized CMOS LC VCO	claim
100	84	Minimax design of nonlinear-phase FIR filters: a least-pth approach	claim
101	84	Recursive patching for video-on-demand (VOD) systems with limited client buffer constraint	claim
102	84	Formulation of INL and DNL yield estimation in current-steering D/A converters	claim
103	84	Buck-boost switched-capacitor DC-DC voltage regulator using delta-sigma control loop	claim
104	84	Design tradeoffs of CMOS current mirrors using one-equation for all-region model	claim
105	84	Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits	claim
106	84	Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method	claim
107	83	Blind equalization by sequential importance sampling	claim
108	83	A necessary and sufficient condition for mismatch shaping in multi-bit DACs	claim
109	83	An embedded DSP core for wireless communication	claim
110	82	Design flow of robust routed power distribution for low power ASIC	claim
111	82	Derivation algorithm of transfer functions of 2-D continuous-discrete systems	claim
112	82	Logic synthesis for PLA with 2-input logic elements	claim
113	82	Delta-sigma algorithmic analog-to-digital conversion	claim
114	82	A hardware accelerator for video segmentation using programmable morphology PE array	claim
115	82	Defining reactive power in circuit transients via local Fourier coefficients	claim
116	82	A novel cost-effective multi-path adaptive interpolated FIR (IFIR)-based echo canceller	claim
117	82	Area-efficient digital baseband module for Bluetooth wireless communications	claim
118	81	Low-voltage analog current detector supporting at-speed BIST	claim
119	81	A ring-processor based blind beamformer design for use in wireless sensor networks	claim
120	81	Concept of phase-noise tuning of bipolar voltage-controlled oscillators	claim
121	80	FRM based FIR filter design - the WLS approach	claim
122	80	Noise-mediated cooperative behavior in a system of coupled DC SQUIDs	claim
123	80	Power line communication front-ends based on ADSL technology	claim
124	79	High-speed pipelined A/D converter using time-shifted CDS technique	claim
125	79	Practical notes on two Volterra filter identification direct methods	claim
126	78	Optimization of portable system architecture for real-time 3D graphics	claim
127	78	HomSSPICE: a homotopy-based circuit simulator for periodic steady-state analysis of oscillators	claim
128	77	Problem dimensionality reduction in design of optimal IIR filters	claim
129	76	A matrix transform imager allowing high-fill factor	claim
130	76	An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels	claim
131	76	Concept of spectrum-signal transformation	claim
132	75	An improved peak-to-average-power ratio reduction algorithm for multicarrier communications	claim
133	75	Non-causal error diffusion for image halftoning	claim
134	74	A generalized methodology for lower-error area-efficient fixed-width multipliers	claim
135	74	Interpolation of discrete periodic nonuniform decimation using alias unraveling	claim
136	72	Delta-sigma modulator topologies with high immunity to pattern noise	claim
137	70	Subspace estimation-based constrained optimization method for multipath CDMA channels	claim
138	69	Fast global motion estimation for sprite generation	claim
139	67	A dynamic frame-skipping video combiner for multipoint video conferencing	claim
140	67	High-selectivity SC filters with continuous digital Q-factor programmability	claim
141	66	A low-noise nonlinear feedback technique for compensating offset in analog multipliers	claim
142	65	Maximum achievable energy reduction using coding with applications to deep sub-micron buses	claim
143	64	Fractional biorthogonal partners and application in signal interpolation	claim
144	62	Joint source-channel content-based multistream video coding scheme	claim
145	61	On the geodesic paths approach to multichannel signal processing	claim
146	60	Low coefficient complexity approximations of the one dimensional discrete cosine transform	claim
147	60	The unified discrete Fourier-Hartley transforms: theory and structure	claim

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