Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors

Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fault tolerance embedded so as to satisfy the fundamental requirement of computational correctness. In this paper an architectural-level computation model is proposed for fault tolerant computations in nanoelectronic processors. The proposed scheme is capable of guaranteeing the correctness of each instruction through exploitation of both hardware and time redundancy, even under high and variable fault rates. Each instruction is confirmed by multiple computation instances. Through a speculative execution based on unconfirmed results, the proposed scheme eliminates the severe performance deterioration typically caused by time redundancy approaches on data dependent instructions. To avoid the exponential growth of resource allocation introduced by the hardware redundancy approaches on the speculations, a hardwa...

• Type: Conference
• Year: 2005
• Where: ICCD
• Authors: Wenjing Rao, Alex Orailoglu, Ramesh Karri
• Keywords: Fault Tolerance, Hardware, ICCD 2005, Time Redundancy, Variable Fault Rates