ICCD 2005 - PDF Preprint Papers

ICCD 2005 International Conference on Computer Design

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ICCD
2005
IEEE

246views Hardware» more ICCD 2005»

H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication

14 years 8 months ago

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FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...

Xizhen Xu, Sotirios G. Ziavras

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Id	Views	Title	Status

1	246	H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication	claim
2	224	Algorithmic and Architectural Design Methodology for Particle Filters in Hardware	claim
3	221	Broadband Impedance Matching for Inductive Interconnect in VLSI Packages	claim
4	176	A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management	claim
5	169	ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology	claim
6	165	Counter-Based Cache Replacement Algorithms	claim
7	165	Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation	claim
8	159	Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors	claim
9	137	Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines	claim
10	135	Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults	claim
11	134	Architectural Considerations for Energy Efficiency	claim
12	134	Analytical Model for Sensor Placement on Microprocessors	claim
13	131	A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs	claim
14	131	Efficient Thermal Simulation for Run-Time Temperature Tracking and Management	claim
15	129	Temperature-Aware Voltage Islands Architecting in System-on-Chip Design	claim
16	128	Automatic Synthesis of Composable Sequential Quantum Boolean Circuits	claim
17	127	Using Scratchpad to Exploit Object Locality in Java	claim
18	124	A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICs	claim
19	124	Accurate Diagnosis of Multiple Faults	claim
20	124	Model Checking C Programs Using F-SOFT	claim
21	121	Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow	claim
22	121	Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration	claim
23	120	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis	claim
24	119	Deployment of Better Than Worst-Case Design: Solutions and Needs	claim
25	116	Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis	claim
26	114	Memory Bank Predictors	claim
27	114	State Set Management for SAT-based Unbounded Model Checking	claim
28	111	Supply Voltage Degradation Aware Analytical Placement	claim
29	111	Low- and Ultra Low-Power Arithmetic Units: Design and Comparison	claim
30	110	Near-memory Caching for Improved Energy Consumption	claim
31	110	Implementing Caches in a 3D Technology for High Performance Processors	claim
32	109	Optimizing the Thermal Behavior of Subarrayed Data Caches	claim
33	109	Reducing the Energy of Speculative Instruction Schedulers	claim
34	109	VALVE: Variable Length Value Encoder for Off-Chip Data Buses.	claim
35	108	Methods for Modeling Resource Contention on Simultaneous Multithreading Processors	claim
36	107	Hardware Support for Bulk Data Movement in Server Platforms	claim
37	102	ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values	claim
38	102	Copyright	claim
39	102	Monitoring Temperature in FPGA based SoCs	claim
40	101	Restrictive Compression Techniques to Increase Level 1 Cache Capacity	claim
41	101	Three-Dimensional Cache Design Exploration Using 3DCacti	claim
42	101	The TM3270 Media-Processor Data Cache	claim
43	100	Temporal Decomposition for Logic Optimization	claim
44	100	Power-Efficient Wakeup Tag Broadcast	claim
45	98	Reducing the Latency and Area Cost of Core Swapping through Shared Helper Engines	claim
46	97	Temperature-Sensitive Loop Parallelization for Chip Multiprocessors	claim
47	97	Dealing with I/O Devices in the Context of Pervasive System Verification	claim
48	96	File System Interfaces for Embedded Software Development	claim
49	92	Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag	claim
50	90	Variability-Driven Buffer Insertion Considering Correlations	claim
51	78	Formal Verification and its Impact on the Snooping versus Directory Protocol Debate	claim
52	63	A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits	claim

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