Architectural Modifications to Enhance the Floating-Point Performance of FPGAs

With the density of FPGAs steadily increasing, FPGAs have reached the point where they are capable of implementing complex floating-point applications. However, their general-purpose nature has limited the use of FPGAs in scientific applications that require floating-point arithmetic due to the large amount of FPGA resources that floating-point operations still require. This paper considers three architectural modifications that make floating-point operations more efficient on FPGAs. The first modification embeds floating-point multiply-add units in an island style FPGA. While offering a dramatic reduction in area and improvement in clock rate, these embedded units have the potential to waste significant silicon for non-floating-point applications. The next two modifications target a major component of IEEE compliant floating-point computations: variable length shifters. The first alternative to LUTs for implementing the variable length shifters is a coarsegrained approach: embedded va...

• Type: Journal
• Year: 2008
• Where: TVLSI
• Authors: Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
• Keywords: Floating-point, FPGA, TVLSI 2008, Variable Length Shifters