Architecture Issues and Solutions for a High-Capacity FPGA

ct High-capacity FPGAs pose device architects with a variety of problems. The most obvious of these problems is interconnect capacity. Others include interconnect performance, clock distribution and IO capacity. This paper describes these problems and the solutions to these problems chosen in the Xilinx XC4000EX family architecture. 2 Overview XC4000EX family of devices extends the architecture of the XC4000 [Hsieh 1990][Trimberger 1994] to larger gate counts. Devices have been announced with over 2300 CLBs and nearly 7000 LUTs. The XC4000EX CLB is compatible with the XC4000E, leveraging eight years of applications and software development. The XC4000EX includes additions and extensions for high-capacity devices [Xilinx 1996]. The basic tiled structure of the XC4000 devices is shown in

• Type: Conference
• Year: 1997
• Where: FPGA
• Authors: Steven Trimberger, Khue Duong, Bob Conn
• Keywords: FPGA, FPGA 1997, Interconnect Capacity, XC4000EX Family, Xilinx XC4000EX Family