Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits

This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, as is done by real-life testers. contribution of the paper is the abstraction of the circuit’s behavior as a synchronous finite state machine in such a way that similar techniques to those currentlyused for synchronous circuits can be safely applied for testing. Currently,the fault model beingusedis the input stuck-at model. Experimental results on different benchmarks show that our approach generates test vectors with high fault coverage.

• Type: Conference
• Year: 1997
• Where: DAC
• Authors: Oriol Roig, Jordi Cortadella, Marco A. Peña, Enric Pastor
• Keywords: Automatic Test Pattern Generation, Computer Architecture, DAC 1997, Synchronous Test Vectors, Synchronous finite State