Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability

Memory accesses have always been a speed-limiting factor, and memory bandwidth has always been an intensively contended scarce resource. Nevertheless, with recent pervasive emergence of portable information appliances, the extraordinary power consumption ratio of memory accesses promotes importance of efficient memory system design to an ultimate. We address the following issues: how to minimize memory bandwidth requirement for instruction accesses, and how to minimize memory access delay, again for instruction accesses. Then we propose to move dynamic branch handler (e.g., branch target buffer) from CPU to the instruction memory side (i.e., bind BTB and instruction memory in the same bus module). We present such a design which can help us

• Type: Conference
• Year: 2006
• Where: CDES
• Authors: Hui-Chin Yang, Chung-Ping Chung
• Keywords: CDES 2006, CDES 2007, Instruction Accesses, Memory Accesses, Memory Bandwidth