Benchmarking and hardware implementation of JPEG-LS

The JPEG-LS algorithm is one of the recently designated standards for lossless compression of grayscale and color images. In this paper, simulation results for lossless and near lossless compression of various image types are presented in order to explore the algorithm's effectiveness for a number of applications. A hardware implementation using VHDL is proposed and the schematic of a JPEG-LS codec, that is capable of standardcompliant lossless and near-lossless encoding and decoding, was generated using the Synopsys synthesis tool. Hardware implementation of the proposed solution on an FPGA allows for real-time processing of large image volumes.

• Type: Conference
• Year: 2002
• Where: ICIP
• Authors: Andreas E. Savakis, Michael D. Piorun
• Keywords: Hardware Implementation, ICIP 2002, Image Processing, Lossless Compression, Synopsys Synthesis Tool