In this paper we present a novel two-stage method to realize a lightweight but very capable hardware implementation of a Learning Classifier System for on-chip learning. Learning C...
Andreas Bernauer, Johannes Zeppenfeld, Oliver Brin...
This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (D...
A performance comparison for the 64-bit block cipher (Triple-DES, IDEA, CAST-128, MISTY1, and KHAZAD) FPGA hardware implementations is given in this paper. All these ciphers are u...
Paris Kitsos, Nicolas Sklavos, Michalis D. Galanis...
Abstract. The large amount of data generated by neuroprosthetic devices requires a high communication bandwidth for extra-cranial transmission, critically limiting the number and u...
We present an algorithm that by using the and -1 Frobenius operators concurrently allows us to obtain a parallelized version of the classical -and-add scalar multiplication algor...
Omran Ahmadi, Darrel Hankerson, Francisco Rodr&iac...
This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions o...
In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consum...
The power of side-channel leakage attacks on cryptographic implementations is evident. Today's practical defenses are typically attack-specific countermeasures against certain...
This paper describes a pattern-based approach to building packet classifiers. One novelty of the approach is that it can be implemented efficiently in both software and hardware. ...
Mary L. Bailey, Burra Gopal, Michael A. Pagels, La...
In recent years the financial world has seen an increasing demand for faster risk simulations, driven by growth in client portfolios. Traditionally many financial models employ Mo...