BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP

Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future chip multi-processor (CMP). However, while NoCs are very efficient for delivering high throughput point-to-point data from sources to destinations, their multi-hop operation is too slow for latency sensitive signals. In addition, current NoCS are inefficient for broadcast operations and centralized control of CMP resources. Consequently, state-of-the-art NoCs may not facilitate the needs of future CMP systems. In this paper, the benefit of adding a low latency, customized shared bus as an internal part of the NoC architecture is explored. BENoC (Bus-Enhanced Network on-Chip) possesses two main advantages: First, the bus is inherently capable of performing broadcast transmission in an efficient manner. Second, the bus has lower and more predictable propagation latency. In order to demonstrate the potential bene...

• Type: Journal
• Year: 2008
• Where: CAL
• Authors: I. Walter, Israel Cidon, Avinoam Kolodny
• Keywords: CAL 2008, Latency Sensitive Signals, Main Interconnect Infrastructure, Nocs, Software Engineering