From Bit Level Systolic Arrays to HDTV Processor Chips

The paper starts presents the work initially carried out by Queen's University and RSRE (now Qinetiq) in the development of advanced architectures and microchips based on systolic array architectures. The paper outlines how this has led to the development of highly complex designs for high definition TV and highlights work both on advanced signal processing architectures and tool flows for advanced systems.

• Type: Conference
• Year: 2006
• Where: ASAP
• Authors: John V. McCanny, Roger F. Woods, John G. McWhirter
• Keywords: Advanced Architectures, ASAP 2006, Hardware, Signal Processing Architectures, Systolic Array Architectures