Buffer insertion for clock delay and skew minimization

 Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer insertion and sizing scheme. Particularly, due to the buffer to buffer delay is a convex function of buffer positions in a clock tree, we show that the minimal clock delay can be obtained by equalizing derivatives of this convex function, and the minimal skew can be obtained by equalizing delay functions of different source to sink paths. Based on this theory, we further develop a three-stage method to initially insert buffers in a given clock routing tree, minimize delay by optimizing buffer positions, and minimize skew by buffer level augment and buffer size refinement. The presented algorithm achieves both minimal delay and skew in real clock tree design.

• Type: Conference
• Year: 1999
• Where: ISPD
• Authors: X. Zeng, D. Zhou, Wei Li
• Keywords: Buffer Insertion, Buffer Positions, Hardware, ISPD 1999, Minimal Clock