ISPD 1999 - PDF Preprint Papers

ISPD 1999 International Symposium on Physical Design

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ISPD
1999
ACM

128views Hardware» more ISPD 1999»

Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis

14 years 4 months ago

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There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...

Michael A. Riepe, Karem A. Sakallah

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Id	Views	Title	Status

1	128	Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis	claim
2	127	Buffer insertion for clock delay and skew minimization	claim
3	126	Partitioning by iterative deletion	claim
4	112	Arbitrary convex and concave rectilinear block packing using sequence-pair	claim
5	109	The deep sub-micron signal integrity challenge	claim
6	108	On the behavior of congestion minimization during placement	claim
7	106	Timing driven maze routing	claim
8	98	Towards synthetic benchmark circuits for evaluating timing-driven CAD tools	claim
9	97	A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design	claim
10	95	Incremental capacitance extraction and its application to iterative timing-driven detailed routing	claim
11	94	Gate sizing with controlled displacement	claim
12	92	Crosstalk constrained global route embedding	claim
13	92	Slicing floorplans with range constraint	claim
14	89	VIA design rule consideration in multi-layer maze routing algorithms	claim
15	88	Subwavelength optical lithography: challenges and impact on physical design	claim
16	85	Optimal partitioners and end-case placers for standard-cell layout	claim
17	83	Efficient solution of systems of orientation constraints	claim
18	79	Partitioning with terminals: a "new" problem and new benchmarks	claim
19	77	Post-routing timing optimization with routing characterization	claim
20	76	A method of measuring nets routability for MCM's general area routing problems	claim
21	69	Interconnect thermal modeling for determining design limits on current density	claim

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