A (partial) Built-In Self-Test (BIST) methodology is proposed for analog to digital (MD)converters. In this methodology the number of bits of the A/Dconverter that needs to be monitored externally in a test is reduced. This reduction depends, among other things, on the frequency of the applied test signal. At low test signal frequencies only the least signipcant bit (LSB) needs to be monitored and a “full”BIST becomes feasible. An analysis is made of the trade-off between the size of the on-chip test circuitry and the accuracy of this BIST technique.
R. de Vries, Taco Zwemstra, E. M. J. G. Bruls, Pau