Cache Aware Mapping of Streaming Applications on a Multiprocessor System-on-Chip

Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottleneck in current and future systems. Cache misses and a large cache miss penalty contribute to a low processor utilisation. In this paper, we describe a novel cache optimisation technique to reduce instruction and data cache misses for streaming applications. The instruction and data locality are improved by executing a task multiple times before moving to the next task. Furthermore, we introduce a dataflow model that is used to trade-off the number of cache misses against end-to-end latency and memory usage. For our industrial application, which is a Digital Radio Mondiale receiver, the number of cache misses is reduced with a factor 4.2.

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: Arno Moonen, Marco Bekooij, Rene van den Berg, Jef L. van Meerbergen
• Keywords: Cache Miss Penalty, Cache Misses, Data Cache Misses, DATE 2008, Hardware