Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison

Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems because of their dynamic and adaptive behavior, and thus need special attention to be used in hard real-time systems. A lot of progress has been achieved in the last ten years to statically predict worst-case execution times (WCETs) of tasks on architectures with caches. However, cache-aware WCET analysis techniques are not always applicable or may be too pessimistic. An alternative approach allowing to use caches in real-time systems is to lock their contents (i.e. disable cache replacement) such that memory access times and cache-related preemption times are predictable. In this paper, we compare the performance of two algorithms for static locking of instruction caches: one using a genetic algorithm for cache contents selection [3] and a pragmatical algorithm, called herafter reference-based algorithm [14...

• Type: Conference
• Year: 2005
• Where: ECRTS
• Authors: Antonio Martí Campoy, Isabelle Puaut, Angel Perles Ivars, José V. Busquets-Mataix
• Keywords: ECRTS 2005, Genetic Algorithm, Reference-based Algorithm, Worst-case Execution