A CAM Emulator Using Look-Up Table Cascades

An address table relates k different registered vectors to the addresses from 1 to k. An address generation function represents the address table. This paper presents a realization of an address generation function with an LUT cascade on an FPGA. The address generation function is implemented by BRAMs of an FPGA, while the addition and the deletion of registered vectors are implemented by an embedded processor on the FPGA. Compared with CAMs produced by the Xilinx Core Generator, our implementations are smaller and faster. This paper also shows that the addition and deletion of a registered vector can be done in time that is proportional to the number of cells in the LUT cascade.

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura
• Keywords: Address Generation Function, Address Table, Distributed And Parallel Computing, IPPS 2007, LUT Cascade