Programmable Numerical Function Generators: Architectures and Synthesis Method

This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal, etc. Our architecture uses an LUT (Look-Up Table) cascade as the segment index encoder, compactly realizes various numerical functions, and is suitable for automatic synthesis. We have developed a synthesis system that converts MATLAB-like specification into HDL code. We propose and compare three architectures implemented as a FPGA (Field-ProgrammableGate Array). Experimental results show the efficiency of our architecture and synthesis system.

• Type: Conference
• Year: 2005
• Where: FPL
• Authors: Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
• Keywords: Architecture, FPL 2005, Numerical Function Generators, Numerical Functions