Cascade Scheme for Concurrent Errors Detection

The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades followed by parity checking their output logic. The algorithm for partitioning the scheme into cascades is provided. An universal scheme of Finite State Machine (FSM) with the cascade errors detection is presented and investigated. The scheme does not require any redundant coding variables. Benchmark results are presented and show significantly low overhead requirement.

• Type: Conference
• Year: 2006
• Where: DSD
• Authors: Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladimir Sinelnikov
• Keywords: Cascade Errors Detection, DSD 2006, Hardware, Redundant Coding Variables, Universal Scheme