DSD 2006 - PDF Preprint Papers

DSD 2006 Euromicro Symposium on Digital Systems Design

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DSD
2006
IEEE

183views Hardware» more DSD 2006»

Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core

14 years 5 months ago

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The Advanced Encryption Standard (AES) algorithm has become the default choice for various security services in numerous applications. In this paper we present an AES encryption h...

Panu Hämäläinen, Timo Alho, Marko H...

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Id	Views	Title	Status

1	183	Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core	claim
2	174	Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering	claim
3	159	Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions	claim
4	135	Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography	claim
5	131	Designing Efficient Irregular Networks for Heterogeneous Systems-on-Chip	claim
6	126	Off-Line Testing of Delay Faults in NoC Interconnects	claim
7	120	Adaptive Power Management for the On-Chip Communication Network	claim
8	116	Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard	claim
9	116	Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*	claim
10	115	Abstract Application Modeling for System Design Space Exploration	claim
11	114	Improved Precision of Coarse Grained Localization in Wireless Sensor Networks	claim
12	113	Lifetime Analysis in Heterogeneous Sensor Networks	claim
13	113	An Asynchronous PLA with Improved Security Characteristics	claim
14	113	Cascade Scheme for Concurrent Errors Detection	claim
15	110	A Flexible, Syntax Independent Representation (SIR) for System Level Design Models	claim
16	110	A Graph Based Algorithm for Data Path Optimization in Custom Processors	claim
17	109	ATOMI II - Framework for Easy Building of Object-oriented Embedded Systems	claim
18	107	A High Level Power Model for the Nostrum NoC	claim
19	99	Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads	claim
20	98	Profiling Bluetooth and Linux on the Xilinx Virtex II Pro	claim
21	95	Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication	claim
22	93	High-Level Decision Diagram based Fault Models for Targeting FSMs	claim
23	90	Global Analysis of Resource Arbitration for MPSoC	claim
24	89	FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar	claim
25	83	Solving the Fundamental Problem of Digital Design - A Systematic Review of Design Methods	claim
26	83	Resource-Efficient Routing and Scheduling of Time-Constrained Network-on-Chip Communication	claim
27	73	Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications	claim
28	72	A Monitoring-Aware Network-on-Chip Design Flow	claim

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