Charge sharing fault analysis and testing for CMOS domino logic circuits

Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic suffers from several design problems and one of the most notable ones is the chargesharing problem. In this paper, we describe a method to measure the sensitivity of the charge-sharing problem for each domino gate. In addition, our algorithm also generates test vectors to detect the worst case of chargesharing fault.

• Type: Conference
• Year: 2000
• Where: ATS
• Authors: Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
• Keywords: ATS 2000, Domino Logic, Domino Logic Design, Domino Logic Suffers, Hardware