ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
: In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed i...
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
An algorithmic fault detection scheme for linear digital state variable systems is proposed. The proposed scheme eliminates the necessity of observing the internal states of the s...
ATS
2000
IEEE
14 years 4 months ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...