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ATS
2000
IEEE
98views Hardware» more  ATS 2000»
14 years 3 months ago
Embedded core testing using genetic algorithms
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...
Ruofan Xu, Michael S. Hsiao
ATS
2000
IEEE
149views Hardware» more  ATS 2000»
14 years 3 months ago
Efficient built-in self-test algorithm for memory
We present a new pseudorandom testing algorithm for the Built-In Self-Test (BIST) of DRAM. In this algorithm, test patterns are complemented to generate state-transitions that are...
Sying-Jyan Wang, Chen-Jung Wei
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
14 years 3 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
ATS
2000
IEEE
57views Hardware» more  ATS 2000»
14 years 3 months ago
Fast hierarchical test path construction for DFT-free controller-datapath circuits
Yiorgos Makris, Jamison Collins, Alex Orailoglu
ATS
2000
IEEE
116views Hardware» more  ATS 2000»
14 years 3 months ago
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
: In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed i...
Said Hamdioui, A. J. van de Goor
ATS
2000
IEEE
86views Hardware» more  ATS 2000»
14 years 3 months ago
An adjacency-based test pattern generator for low power BIST design
Patrick Girard, Loïs Guiller, Christian Landr...
ATS
2000
IEEE
145views Hardware» more  ATS 2000»
14 years 3 months ago
Compaction-based test generation using state and fault information
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwa...
ATS
2000
IEEE
107views Hardware» more  ATS 2000»
14 years 3 months ago
Accumulation-based concurrent fault detection for linear digital state variable systems
An algorithmic fault detection scheme for linear digital state variable systems is proposed. The proposed scheme eliminates the necessity of observing the internal states of the s...
Ismet Bayraktaroglu, Alex Orailoglu
ATS
2000
IEEE
149views Hardware» more  ATS 2000»
14 years 3 months ago
Charge sharing fault analysis and testing for CMOS domino logic circuits
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Sh...